(1) Field of the Invention
The invention relates to a method for forming silicon-on-insulator substrates, and more particularly to a method for accurately controlling the thickness and uniformity of the top silicon layer for silicon-on-insulator technology applications.
(2) Description of the Related Art
Dielectric isolation of semiconductor devices has proven to be effective for improving several important device parameters. In particular, Silicon-on-Insulator (SOI) technology offers good isolation, reduced short channel effects, radiation hardness, high voltage breakdown, and high-speed circuitry. Typically, semiconductor islands are isolated from each other with a vertical dielectric, and have a bottom surface that is adjacent to a horizontal dielectric layer as well. Semiconductor devices are then formed in the semiconductor islands.
Several methods have been described for providing dielectric isolation. In one method, known as SIMOX (Separation by IMplanted OXygen), oxygen atoms are implanted at a very high energy into a single-crystal silicon substrate, followed by an annealing step, thereby forming a horizontal layer of silicon oxide at a depth below the surface of the substrate. However, there typically is damage to the substrate in the form of severe dislocations as a result of the implant. One of the most promising SOI approaches is bonded-wafer technology, as described, for instance, by J. B. Lasky et al in "Bonding and Etch-Back, Silicon-On-Insulator", pp. 684-687, IEDM 1985. Two substrates of single-crystal silicon, each with one oxidized surface, are bonded together at the oxidized surfaces. Lapping is then performed on one of the silicon substrates to reduce its thickness.
However, the desired thicknesses need to be on the order of 1 micron or less, in order to reduce parasitic capacitance and increase circuit speed. Lapping to this small a thickness is difficult due to variations in the smoothness and uniformity of the semiconductor surface being worked. One solution is shown in U.S. Pat. No. 5,091,330 (Cambou et al), in which a dielectric is formed in trenches in one of the two bonded substrates, prior to bonding, and is used as an etch stop for chemical/mechanical polishing to provide a thin semiconductor layer for the formation of devices.